Embedded systems are often subject to tighter power constraints due to their portable nature and increased dependence on batteries. Previous studies have shown that the instruction cache can be responsible for a significant portion of the energy consumption. Although traditional caches are often found on embedded processors, some also include specialized cache structures to further reduce energy requirements. Such specialized cache structures include filter/L0 instruction caches. A filter/L0 instruction cache is typically placed in series before the L1 instruction cache. Since the filter/L0 instruction cache is accessed instead of the L1 instruction cache (L1-IC), any miss in the filter/L0 instruction cache incurs an additional I-cycle miss penalty prior to fetching the appropriate line from the L1-IC. Although a filter/L0 instruction cache reduces the requirements for fetch energy, these miss penalties can accumulate and result in significant performance degradation.
Accordingly, there is a need in the industry for lookahead instruction fetching for processors.